Development of a DMILL radhard multiplexer for the ATLAS Glink optical link and radiation test with a custom Bit ERror Tester

A high speed digital optical data link has been developed for the front-end readout of the ATLAS electromagnetic calorimeter. It is based on a commercial serialiser commonly known as Glink, and a vertical cavity surface emitting laser. To be compatible with the data interface requirements, the Glink must be coupled to a radhard multiplexer that has been designed in DMILL technology to reduce the impact of neutron and gamma radiation on the link performance. This multiplexer features a very severe timing constraints related both to the front-end board output data and the Glink control and input signals. The full link has been successfully neutron and proton radiation tested by means of a custom bit error tester. (7 refs)

A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout

The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 3 analog channels through one analog to digital converter. It is a first step for a multiplexed 64 channel design. A CMOS 0.35μm process is used. The dynamic range is 2V over a 3.3V power supply, and the total power dissipation at 25 MHz is approximately 40mW. An analog power management is included to allow a fast switching into a standby mode that reduces the DC power dissipation by a ratio of three orders of magnitude (1/1000)

Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics

The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design

Development of a front end ASIC for Dark Matter directional detection with MIMAC

A front end ASIC (BiCMOS-SiGe 0.35 \mum) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (a few keV) tracks with a gaseous \muTPC. The development of this front end ASIC is a key point of the project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronics. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2 x 96 strips of pixels are monitored.Comment: 12 pages, 10 figure

Experimental study of a liquid Xenon PET prototype module

A detector using liquid Xenon in the scintillation mode is studied for Positron Emission Tomography (PET). The specific design aims at taking full advantage of the liquid Xenon properties. It does feature a promising insensitive to any parallax effect. This work reports on the performances of the first LXe prototype module, equipped with a position sensitive PMT operating in the VUV range (178 nm).Comment: Proc. of the 7th International Workshops on Radiation Imaging Detectors (IWORID-7), Grenoble, France 4-7 July 200

Electronic tests of the barrel presampler mother boards

The electrical characteristics of the barrel presampler mother boards are recalled. The results of the tests of the first full-size mother board are presented. They satisfy our specifications

Electrical tests of e. m. barrel presampler sectors

A description of the tests and electronics used to control the presampler sectors, before and after their assembly, is given. An example of the results obtained for the first two sectors, tested at room and liquid nitrogen temperatures, is shown

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for monolithie active pixel sensors

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide